1. Field of the Invention
The invention relates generally relates to semiconductor devices. More particularly, the invention relates to an overlay accuracy measurement vernier and a method of forming the same, in which a step necessary to measure overlay accuracy is formed after a planarization process in the process of forming a trench of a region in which the overlay accuracy measurement vernier is formed, thereby preventing overlay accuracy measurement error.
2. Discussion of Related Art
In general, a semiconductor device includes a cell region in which a cell for storing data is formed and a peri region in which a circuit element for driving the cells is formed. In the manufacturing process of the semiconductor device, a vernier is used to measure overlay accuracy between an etch process of a first layer and an etch process of a second layer. The overlay accuracy measurement vernier may be formed in a part of the peri region or a scribe line. Hereinafter, a region in which the overlay accuracy measurement vernier will be formed will be described independently from the peri region.
Meanwhile, in flash memory devices that store and erase data through tunneling, a dual trench structure is employed in which trenches for forming isolation films are formed to have different widths and depths in the cell region and the peri region in devices of 70 nm or less, in order to secure a breakdown voltage of an insulating film gap-fill process and a high voltage region.
In the flash memory device employing the dual trench structure as described above, when the trenches are formed in the peri region, a dual trench is formed in such a manner that the trenches are also formed in a region in which the overlay accuracy measurement vernier will be formed and are then formed in the cell region. An insulating film is formed to bury the trenches and is then polished to form the isolation films in the cell region and the peri region. A key open process of the overlay accuracy measurement vernier formation region is then performed.
However, since the trench of the vernier region and the trench of the peri region are formed at the same time, the depth of the trench in the two regions is the same. Accordingly, after a polishing process of the insulating film for forming the isolation film, the vernier is not properly formed in the key open process. As a result, when a mask for an etch process is formed after an opaque film such as a polysilicon film or a tungsten film is deposited, the overlay accuracy measurement vernier is not seen. Accordingly, a problem arises because error is caused or measurement itself is impossible upon overlay accuracy measurement.